These are the most frequently used words in this book.
address
analysis
analyzer
between
bit
case
chip
circuit
clock
combinational
consider
control
controllability
cycle
data
delay
design
detect
detection
different
either
equation
error
example
fault
feedback
figure
first
function
gate
generator
given
however
input
latch
length
let
lfsr
line
linear
logic
masking
may
memory
method
misr
must
network
node
number
observability
occur
operation
output
parity
part
path
pattern
points
polynomial
possible
primary
probability
problem
procedure
random
register
requires
response
results
scan
sequence
set
shift
shown
shows
signal
signature
since
single
srl
stage
state
step
structure
system
table
terms
test
testability
testing
thus
time
transition
two
use
used
values
vector
x2
