- Paperback: 566 pages
- Publisher: Springer; Softcover reprint of hardcover 1st ed. 2000 edition (Dec 7 2010)
- Language: English
- ISBN-10: 3642086918
- ISBN-13: 978-3642086915
- Product Dimensions: 23.5 x 18.4 x 3.3 cm
- Shipping Weight: 1 Kg
- See Complete Table of Contents
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Product Details |
Product Description
Product Description
Hardware correctness is becoming ever more important in the design of computer systems. The authors introduce a powerful new approach to the design and analysis of modern computer architectures, based on mathematically well-founded formal methods which allows for rigorous correctness proofs, accurate hardware costs determination, and performance evaluation. This book develops, at the gate level, the complete design of a pipelined RISC processor with a fully IEEE-compliant floating-point unit. In contrast to other design approaches, the design presented here is modular, clean and complete.
Book Info
Develops, at the gate level, the design of a pipelined RISC processor with delayed branch, forwarding, hardware interlock, precise maskable nested interrupts, caches, and a fully IEEE-compliant floating point unit. A textbook for computer science students.
--This text refers to the
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First Sentence
In this book we develop at the gate level the complete design of a pipelined RISC processor with delayed branch, forwarding, hardware interlock, precise maskable nested interrupts, caches, and a fully IEEE-compliant floating point unit. Read the first page Browse Sample Pages
Front Cover | Copyright | Table of Contents | Excerpt | Index | Back Cover
In this book we develop at the gate level the complete design of a pipelined RISC processor with delayed branch, forwarding, hardware interlock, precise maskable nested interrupts, caches, and a fully IEEE-compliant floating point unit. Read the first page Browse Sample Pages
Front Cover | Copyright | Table of Contents | Excerpt | Index | Back Cover
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