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Guide to RISC Processors: for Programmers and Engineers [Hardcover]

Sivarama P. Dandamudi

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Book Description

March 21 2005 0387210172 978-0387210179 2005
Details RISC design principles as well as explains the differences between this and other designs.
Helps readers acquire hands-on assembly language programming experience

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Product Description

From the Back Cover

Recently, there has been a trend toward processor design based on the RISC (Reduced Instruction Set Computer) model: Example RISC processors are the MIPS, SPARC, PowerPC, ARM, and even Intel’s 64-bit processor Itanium.

This guidebook provides an accessible and all-encompassing compendium on RISC processors, introducing five RISC processors: MIPS, SPARC, PowerPC, ARM, and Itanium. Initial chapters explain the differences between the CISC and RISC designs and clearly discuss the core RISC design principles. The text then integrates instruction on MIPS assembly language programming, thereby enabling readers to concretely grasp concepts and principles introduced earlier. Readers need only have a basic knowledge of any structured, high-level language to obtain the full benefits here.

Features:

*Includes MIPS simulator (SPIM) download instructions, so that readers can get hands-on assembly language programming experience

*Presents material in a manner suitable for flexible self-study

• Assembly language programs permit reader executables using the SPIM simulator

• Integrates core concepts to processor designs and their implementations

• Supplies extensive and complete programming examples and figures

• Contains chapter-by-chapter overviews and summaries

* Provides source code for the MIPS language at the book’s website

Guide to RISC Processors provides a uniquely comprehensive introduction and guide to RISC-related concepts, principles, design philosophy, and actual programming, as well as the all the popular modern RISC processors and their assembly language. Professionals, programmers, and students seeking an authoritative and practical overview of RISC processors and assembly language programming will find the guide an essential resource.

Sivarama P. Dandamudi is a professor of computer science at Carleton University in Ottawa, Ontario, Canada, as well as associate editor responsible for computer architecture at the International Journal of Computers and Their Applications. He has more than two decades of experience teaching about computer systems and organization. 

 

Key Topics

* Processor design issues

* Evolution of CISC and RISC processors

* MIPS, SPARC, PowerPC, Itanium, and ARM architectures

* MIPS assembly language

* SPIM simulator and debugger

* Conditional execution

* Floating-point and logical and shift operations

* Number systems

 

 

Computer Architecture/Programming

Beginning/Intermediate Level


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Amazon.com: 5.0 out of 5 stars  1 review
5.0 out of 5 stars Excellent introduction to RISC processors. Aug. 25 2013
By Carlos Sencion - Published on Amazon.com
Format:Hardcover|Verified Purchase
This book is a good introduction to some characteristics of RISC processors. It doesn't cover a lot of internal aspects of the RISC processors hardware, but it does cover a lot of ISA details. Comparition between RISC and CISC appears along the book; including some examples of RISC processor achitectures, such as SPARC and ARM.

The book author asumes some knowledge of assembler, basic C programming language and some terminology of processors from the reader; in order to dive some chapters. The way he explain concepts is not specifically for a newbie. As he exposed, the target audience of the book are professional people and intermediate students of Computer Science or related fields. Skip this book if you lack of the mentioned requeriments or similar knowledge.

Sadly, the book is relatively old(2005). Some of the example RISC processors are from that era. But the main theory remains almost the same as of today(RISC).

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