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Logic Synthesis and Verification Algorithms
 
 

Logic Synthesis and Verification Algorithms [Paperback]

Gary D. Hachtel , Fabio Somenzi
3.3 out of 5 stars  See all reviews (3 customer reviews)
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This book blends mathematical foundations and algorithmic developments with circuit design issues. Each new technique is presented in the context of its application to design. Through the study of optimal two-level and multilevel combinational circuit design, the reader is introduced to basic concepts, such as Boolean algebras, local search, and algebraic factorization. Similarly, through the study of optimal sequential circuit design, the reader is introduced to graph algorithms, finite state systems, and language theory. Throughout the book, recurrent themes such as branch and bound, dynamic programming, and symbolic implicit enumeration are used to establish optimal design principles.

From the Back Cover

In the last decade logic synthesis has gained widepsread acceptance by designers.  Formal verification is now advancing along the same path.  Computer aided design tools for logic synthesis and verification have become the primary instrument for coping with the ever increasing complexity of designs, and ever more stringent time-to-market constraints.  Effective design must be based on thorough understanding of the capabilities, limitations, and algorithmic principles employed by these tools.  In this book we provide a foundation for such understanding. Logic Synthesis and Verification Algorithms blends mathematical foundations and algorithmic developments with circuit design issues.  Each new technique is presented in the context of its application to design.  Through the study of optimal two-level and multilevel combinational circuit design, the reader is introduced to basic concepts, such as Boolean algebras, local search, and algebraic factorization. Similarly, through the study of optimal sequential circuit design, the reader is introduced to graph algorithms, finite state systems, and language theory.  Throughout the book, recurrent themes such as branch and bound, dynamic programming, and symbolic implicit enumeration are used to establish optimal design principles. Circuit designers and CAD tool developers alike will find Logic Synthesis and Verification Algorithms useful as an introductory and reference text.  The rich collection of examples and solved problems make this book ideal for self study. Because of its careful balance of theory and application, Logic Synthesis and Verification Algorithms will serve well as a textbook for upper division and first year graduate students in electrical and computer engineering.

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Front Cover | Copyright | Table of Contents | Excerpt | Index | Back Cover
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Average Customer Review
3.3 out of 5 stars (3 customer reviews)
 
 
 
 
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1.0 out of 5 stars I STILL DO NOT HAVE THE BOOK I ORDERED, Feb 8 2011
This review is from: Logic Synthesis and Verification Algorithms (Paperback)
Hi I have ordered this book since more than 1 month. The class for which I needed it is about to finish and I still do not have the book.

At least I hope amazon does a refund on the amount I paid for this.

David
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5.0 out of 5 stars exceptional..., July 7 2004
By A Customer
This book is good. It covers all the fundamentals needed to learn two level and multi level logic synthesis and verification.

It's a good stepping stone for those readers wanting to delve more into the IEEE publications area later on in their careers when implementing new algorithms for logic synthesis.

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4.0 out of 5 stars nachiketh potlapally, Aug 22 2000
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I had the oppurtunity to study this book in my graduate study. I think it is a well-written book, which has a substantial coverage of the field of logic synthesis and verification. I would highly recommend this book to advanced readers and those who are mathematically inclined. The expertise of the authors is reflected in the content of the book, and this can be fully appreciated by the readers having the qualifications mentioned above.
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