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Product Description
The updated second edition of this book provides practical information for hardware and software engineers using the SystemVerilog language to verify electronic designs. The author explains methodology concepts for constructing testbenches that are modular and reusable. The book includes extensive coverage of the SystemVerilog 3.1a constructs such as classes, program blocks, randomization, assertions, and functional coverage. This second edition contains a new chapter that covers programs and interfaces as well as chapters with updated information on directed testbench and OOP, layered, and random testbench for an ATM switch.
From the Back Cover
New! Expanded! Updated! Based on the bestselling first edition this extensively revised second edition includes the relevant changes that apply to the 2008 version of the SystemVerilog Language Reference Manual (LRM). Significant changes include: The revision of nearly every explanation and code sample The inclusion of new chapters: "A Complete SystemVerilog Testbench" with a complete constrained random testbench for an ATM switch and "Interfacing with C" on the DPI (Directed Programming Interface) The addition of 70 new examples including larger ones such as a directed testbench at the end of chapter four An expanded index with 50% more entries and cross references "As digital integrated circuits relentlessly march towards a billion transistors and beyond, Verilog testbenches are running out of steam. With logic verification taking more effort than design, moving to a higher level of abstraction is the only choice. SystemVerilog appears to be the winner in the high-level verification language market and "SystemVerilog for Verification" is the book that will take working professionals and students alike from basic Verilog to the sophisticated structures needed to verify large and complex designs." Ronald W. Mehler, Professor of Electrical and Computer Engineering, California State University Northridge "It can be difficult to improve upon a great book, but Chris has achieved that goal - the second edition of this book is even better than the first! The explanations of abstract verification constructs are more detailed, and many more comprehensive examples make it easier to see how to apply SystemVerilog in object-oriented verification. The new chapter on the SystemVerilog Direct Programming Interface (DPI) is a very valuable addition. This second edition is a must-have book for every engineer involved in Verilog and SystemVerilog design and verification. The book serves well both as a general SystemVerilog reference and for learning object-oriented verification techniques. This book is such an invaluable reference, that my company includes a copy as part of the student training materials with every SystemVerilog verification course we teach!" Stuart Sutherland, SystemVerilog Training Consultant, Sutherland HDL, Inc. Chris Spear is a Verification Consultant for Synopsys, and has advised companies around the world on testbench methodology. He has trained hundreds of engineers on SystemVerilog’s verification constructs. Testbenches are growing more complex. You need this book to keep up. Includes nearly 500 code samples and 70 figures.
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Most helpful customer reviews
5.0 out of 5 stars
SystemVerilog Testbenches OOP aspect explained,
By Miodrag Rozman (Kanata, Ontario Canada) - See all my reviews
This review is from: SystemVerilog for Verification: A Guide to Learning the Testbench Language Features (Hardcover)
This book follows the best tradition of Springer's (publisher) titles covering Systemverilog language. The text clarity, organization and presentation is very solid. This is in-depth technical book on the Systemverilog testbench development, written for intermediate to high end users. It covers in proper detail the transition from Verilog to Systemverilog. The focus is on changing the designer's mindset from RTL and procedural type of constructs mostly found in Verilog to a high-level, object oriented way of thinking when creating more complex functional tests. There are plenty of small code examples (snippets) along with topic descriptions as well as the complete test bench example that summarizes and explains most language features described in the book. This book is a perfect companion and logical continuation of the other book in the same series (Janick Bergeron: "Writing testbenches in Systemverilog"; Springer).
This book alone is not a complete language reference (that would require much more space), but is very good starting point for learning and using the language with it's extensive set of features applicable to complex test-benches.
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Most Helpful Customer Reviews on Amazon.com (beta) Amazon.com:
4.2 out of 5 stars (12 customer reviews) 5 of 5 people found the following review helpful:
4.0 out of 5 stars
Excellent book except for ...,
By Timothy H. Pylant - Published on Amazon.com
This review is from: SystemVerilog for Verification: A Guide to Learning the Testbench Language Features (Hardcover)
a few non-compliant code examples that do not follow the IEEE LRM. With that said, overall the book contains a number of good examples and covers the SV language. It doesn't spend much time discussing methodology (which can be good or bad depending on what you're looking for).
In summary, decent reading and a good language reference. Definitely a lot better than the VMM book. 2 of 2 people found the following review helpful:
5.0 out of 5 stars
Excellent book for systemVerilog newbie,
By S. Li - Published on Amazon.com
This review is from: SystemVerilog for Verification: A Guide to Learning the Testbench Language Features (Hardcover)
This is an excellent systemVerilog introduction book, if you are experienced verilog user want to learn systemVerilog, this book is the right one for you. Highly recommend to anyone who want to utilize systemVerilog features to enhance their current verification environment.
1 of 1 people found the following review helpful:
5.0 out of 5 stars
Excellent Starter Book For Newbies,
By E. Hamel "EMH_007" - Published on Amazon.com
This review is from: SystemVerilog for Verification: A Guide to Learning the Testbench Language Features (Hardcover)
I purchased this book since I had to implement a new verification environment from scratch. I read the entire book, and I was off building a verification environment with SV.
There are few details which are not discussed in the book, for instance how to import classes into other classes(from a package), and how you should compile the entire project (again from a package). Overall, if you don't know SV, and OOP, this is an excellent book to start with. |
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