Verilog Digital Computer Design: Algorithms Into Hardware [Paperback]

For introductory-level courses in Verilog Hardware Description Language. Written by the co-developer of the Verilog Implicit To One hot (VITO) preprocessor, this text introduces the industry standard Verilog Hardware Description Language as a new way to explore enduring concepts in digital and computer design, such as pipelining. It shows how Verilog simulation is a tool for uncovering bugs prior to hardware fabrication, and how Verilog synthesis is a tool for automatically converting source code into hardware. Ideal for designers new to Verilog, it features a consistent design framework using ASM charts, and contains many realistic, practical examples.

Preface

When I started teaching Verilog to electrical engineering and computer science seniors at the University of Wyoming, there were only two books and a handful of papers on the subject, in contrast to the overwhelming body of academic literature written about VHDL. Previously, VHDL had been unsuccessful in this course. For all its linguistic merits, VHDL is too complex for the first-time user. Verilog, on the other hand, is much more straightforward and allows the first-time user to focus on the design rather than on language details. Yet Verilog is powerful enough to describe very exotic designs, as illustrated in chapters 8-11.

As its subtitle indicates, this book emphasizes the algorithmic nature of digital computer design. This book uses the manual notation of Algorithmic State Machine (ASM) charts (chapter 2) as the master plan for designs. This book uses a top-down approach, which is based on the designerÕs faith that details can be ignored at the beginning of the design process, so that the designer's total effort can be to develop a correct algorithm.

Chapters 2-11 use the same elementary algorithm, referred to as the childish division algorithm, for many hardware and software examples. Because this algorithm is so simple, it allows the reader to focus on the Verilog and computer design topics being covered by each chapter. This book is unique in showing the correspondence of ASM charts to implicit style Verilog (chapters 3, 5 and 7). All chapters emphasize a feature of Verilog, known as non-blocking assignment or Register Transfer Notation (RTN), which is the main distinction between software and synchronous hardware. Except for chapter 6, this book ignores (abstracts away) propagation delay. Instead, the emphasis here is toward designs that are accurate on a clock cycle by clock cycle basis with non-blocking assignment. (Many existing Verilog books either provide too much propagation delay information or are so abstract as to be inaccurate on a clock cycle basis. Appendices C and D motivate the abstraction level used here.)

Chapter 4 gives a novel three-stage design process (behavioral, mixed, structural), which exercises the reader's understanding of many elementary features of Verilog. Chapter 7 explains an automated one hot preprocessor, known as VITO, that eliminates the need to go though this manual three-stage process.

This book defers the introduction of Mealy machines until chapter 5 because my experience has been that the complex interactions of decisions and non- blocking assignments in a Mealy machine are confusing to the first-time designer. Understanding chapter 5 is only necessary to understand chapters 9 and 10, appendix J and sections 7.4 and 11.6.

The goal is to emphasize a few enduring concepts of computer design, such as pipelined (chapters 6 and 9) and superscalar (chapter 10) approaches, and show that these concepts are a natural outgrowth of the non-blocking assignment. Chapter 6 uses AS M charts and implicit Verilog to describe pipelining of a special-purpose machine with only the material of chapter 4. Chapters 8, 9 and 11 use the classic PDP-8 as an illustration of the basic principles of a stored program computer and cache memory. Chapter 8 depends only on the ASM material of chapter 2. Chapter 9 requires an understanding of all preceding chapters, except chapter 7. The capstone of this book, chapter 10 (which depends on chapter 9), uses the elegant ARM instruction set to explore the RISC approach, again with the unique combination of ASMs, implicit Verilog and non-blocking assignment.

Chapters 3-6, 9 and 10 emphasize Verilog simulation as a tool for uncovering bugs in a design prior to fabrication. Test code (sometimes called a testbench) that simulates the operating environment for the machine is given with most designs. Chapter 10 introduces the concept of Verilog code coverage. Chapters 7 and 11, which are partially accessible to a reader who understands chapter 3, uses specific synthesis tools for programmable logic to illustrate general techniques that apply to most vendors' tools. Even in synthesis, simulation is an important part of the design flow. Chapter 11 will be much more meaningful after the reader has grasped chapters 1-9.

Appendices A, B and G give background on the machine language examples used in chapters 8-11. Appendices C and D give the block diagram notation used in all chapters for combinational logic and sequential logic, respectively. Chapters 1-11 do not use tri-state bidirectional buses, but appendix E explains the Verilog coding of such buses.

This book touches upon several different areas, such as “computer design,” “state machine design,” “assembly language programming,” “computer organization,” “computer arithmetic,” “computer architecture,” “register transfer logic design,” “hardware/software trade-offs,” “VLSI design,” “parallel processing” and “programmable logic design.” I would ask the reader not to try to place this book into the pigeon hole of some narrow academic category. Rather, I would hope the reader will appreciate in all these digital and computer design topics the common thread which the ASM and Verilog notations highlight. This book just scratches the surface of computer design and of Verilog. Space limitations prevented inclusion of material on interfacing (other than section 11.6) and on multiprocessing. The examples of childish division, PDP-8 and ARM algorithms were chosen for their simplicity. Sections labeled “Further reading” at the end of most chapters indicate where an interested reader can find more advanced concepts and algorithms, as well as more sophisticated features of Verilog. Appendix F indicates postal and Web addresses for obtaining additional tools and resources. It is hoped that the simple examples of Verilog and ASMs in this book will enable the reader to proceed to these more advanced computer design concepts.

In places, this book states my opinions rather boldly. I respect readers who have differing interpretations and methodologies, but I would ask such readers to look past these distinctions to the unique and valuable approaches in this book that are not found elsewhere. I have sprinkled (somewhat biased) historical tidbits, primarily from the first quarter century of electronic computer design, to illustrate how enduring algorithms are, and how transient technology is. Languages are more algorithmic than they are technological. Just look at the endurance of the COBOL language for business software. Hardware description languages will no doubt change as the twenty-first century unfolds, but I suspect whatever they become, they will include something very much like contemporary implicit style Verilog.