The 1998 copyright date is at least six Moore generations ago, as of this writing. CAD tools, and synthesis in particualar, have advanced hugely since then, so much of Bhasker's advice simply isn't needed any more - compilers have gotten lots smarter about common subexpressions, for example, so things like manually factoring them out won't have nearly the impact today that they did then.
Also, for some reason, Bhasker seemed to assume only synthesis straight to silicon when, even then, FPGAs were a significant part of the logic market. In the decade since, synthesis for FPGAs has become the dominant model. That means that synthesis tools need to infer uses of block RAMs, hard multipliers, and other special functions from the HDL code, things outside of Bhasker's discussion. The biggest problem might be timing - it just never gets mentioned, even though it's a major headache in most non-trivial designs.
Perhaps, in its day, thie offered a reasonable introduction for the digital ASIC designer. That day passed, and this just doesn't meet the needs of most current logic implementors.