Verilog Hdl Synthesis: A Practical Primer Paperback – Aug 31 1998
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Most Helpful Customer Reviews on Amazon.com (beta)
My goal was to be able to generate synthsizable Verilog without a lot of experimentation.
The style is by example. It is a good source of useful Verilog coding.
It is assumed you have some background in Verilog.
The book could use some tables on logic operators.
I think people who want to learn and use Verilog for synthesizable designs would benifit from having this book close at hand. It could be a really useful text for college students.
Also, for some reason, Bhasker seemed to assume only synthesis straight to silicon when, even then, FPGAs were a significant part of the logic market. In the decade since, synthesis for FPGAs has become the dominant model. That means that synthesis tools need to infer uses of block RAMs, hard multipliers, and other special functions from the HDL code, things outside of Bhasker's discussion. The biggest problem might be timing - it just never gets mentioned, even though it's a major headache in most non-trivial designs.
Perhaps, in its day, thie offered a reasonable introduction for the digital ASIC designer. That day passed, and this just doesn't meet the needs of most current logic implementors.